Renesas Electronics /R7FA6M4AF /SCI0 /FRDRH

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Interpret as FRDRH

7 43 0 0 00 0 0 0 0 0 0 0 0 (0)MPB 0 (0)DR 0 (0)PER 0 (0)FER 0 (0)ORER 0 (0)RDF

DR=0, MPB=0, FER=0, PER=0, ORER=0, RDF=0

Description

Receive FIFO Data Register

Fields

MPB

Multi-Processor Bit Flag

0 (0): Data transmission cycle

1 (1): ID transmission cycle

DR

Receive Data Ready Flag

0 (0): Receiving is in progress, or no received data remains in the FRDRH and FRDRL registers after successfully completed reception

1 (1): Next receive data is not received for a period after successfully completed reception

PER

Parity Error Flag

0 (0): No parity error occurred in the first data of FRDRH and FRDRL

1 (1): Parity error occurred in the first data of FRDRH and FRDRL

FER

Framing Error Flag

0 (0): No framing error occurred in the first data of FRDRH and FRDRL

1 (1): Framing error occurred in the first data of FRDRH and FRDRL

ORER

Overrun Error Flag

0 (0): No overrun error occurred

1 (1): Overrun error occurred

RDF

Receive FIFO Data Full Flag

0 (0): The amount of receive data written in FRDRH and FRDRL is less than the specified receive triggering number

1 (1): The amount of receive data written in FRDRH and FRDRL is equal to or greater than the specified receive triggering number

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